This invention relates generally to methods for object-oriented hardware design and to hardware produced thereby, and more particularly to distributed memory, object-oriented, class-based methods for processor design and the processors produced thereby.
Voice over Internet protocol (VoIP), wideband code division multiple access (WCDMA), third generation wireless networks, and other advanced wireless and wired broad-band communication systems require many complex, computationally-intensive signal processing functions. Examples of such functions include orthogonal frequency division multiplexing (OFDM) modems, Viterbi decoders, and Reed-Solomon decoders. In many cases, it is desirable for these signal processing functions to be fabricated on a single-chip integrated circuit.
One known methodology for placing such highly complex systems on a single chip is to provide powerful computational platforms on the chip to process all functions in a sequential manner in conjunction with a number of tightly-coupled intellectual property (IPs) cores, i.e., special-purpose processor and firmware layouts that are licensed for use in chip layouts for more complex processors. Computational platforms used in this design methodology include one or more microprocessors or digital signal processors (DSPs) and one or more standard or proprietary communication backbones, interface buses, or virtual sockets to connect all the necessary components into a unified environment. Such platforms can be characterized as being “processor-centric,” because the various processors and IP cores share complex bus architectures to process all of the functions and algorithms sequentially. As systems become larger and more complex, even more powerful core processors are required.
Although presently known signal processing architectures and design methodologies are sufficient for many present applications, it is becoming increasingly difficult to meet processing demands of new applications with these architectures for several reasons. First, newer bus and controller architectures have become very complicated because memory speed cannot keep up with the increasing speed of central processing units (CPU), even with cache memory. Thus, there is a CPU-memory bottleneck that manifests itself in faster applications due to physical propagation factors whenever the silicon die area used by a processor is sufficiently large. Second, present architectures require a costly investment in very large and complex software. When suitable software is written, it is necessarily operating system (OS) dependent, because such dependency is required to ensure that each process receives an appropriate time slice of the CPU's computational resources. Whenever changes to a processor are necessary or a move is made to another OS platform, the prior effort and investment in developing the application software are largely wasted or rendered obsolete. Third, computational demands on processor-centric architectures require increased computational speed as the processes themselves become more complex. Increases in computational speed necessarily raise power consumption.
It would therefore be desirable to provide methods for designing complex application processors that avoid CPU memory bottlenecks due to large silicon die areas. It would also be desirable to provide a processor architecture that provides reduced dependence upon an operating system of any particular core processor and a design method that provides greater freedom to redesign the application processor around a different host processor. It would also be desirable to provide an application processor architecture in which smaller functional sets not requiring a single high-speed processor are performed relatively independently of one another, thereby avoiding the CPU-memory bottleneck.